The escalating requirements for high density and performance associated with ultra-large scale integration semiconductor devices necessitate design features of 0.18 micron and under, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput. The reduction of design features to 0.18 micron and under challenges the limitations of conventional interconnection technology, including conventional photolithographic, etching, and deposition techniques.
Conventional methodology for forming patterned metal layers comprises a subtractive etching or etch back step as the primary metal forming technique. Such a method involves the formation of a first dielectric layer on a semiconductor substrate, typically monocrystalline silicon (Si), with conductive contacts formed therein for electrical connection with at least one active region formed in or on the substrate, such as a source/drain region of a transistor. A metal layer is deposited on the first dielectric layer and patterned using photolithographic masking and etching techniques to form a desired conductive pattern comprising metal features separated by gaps, such as a plurality of metal lines with interwiring spacings therebetween. A dielectric layer is then applied to the resulting conductive pattern to fill in the gaps and the surface thereof is then planarized by conventional etching or chemical-mechanical polishing (CMP) techniques.
A through-hole is then formed in the dielectric layer to expose a selected portion of an underlying metal feature, the exposed portion of the metal feature at the bottom of the through-hole serving as a contact pad. Upon filling the through-hole with conductive material, such as a metal plug, to form a conductive via, the bottom surface of the conductive via is in electrical contact with the underlying metal feature.
Because many ultra large scale integration (ULSI) devices presently manufactured are very complex and require multiple levels of metallization for interconnections, it has been common to repeat the above-described via formation process multiple times, e.g., to form five levels of metallization interconnected by conductive vias, each level of metallization separated by at least one layer of dielectric material, termed an inter-level dielectric (ILD) layer.
A problem encountered in highly miniaturized semiconductor devices employing multiple metallization levels and reduced interwiring spacings in both the horizontal and vertical dimensions is related to the resistance-capacitance (RC) time constant of the system. Although semiconductor devices are presently being scaled in the horizontal dimension, they are not generally scaled in the vertical dimension, since scaling in both dimensions would lead to a higher current density that could exceed reliability limits. Horizontal scaling, however, requires conductive lines having a high aspect ratio, i.e., ratios of conductor height to conductor width greater than one, e.g., three or four, along with reduced interwiring spacings. As a consequence, capacitive coupling between conductive lines becomes a significant limitation on circuit speed. If intrametal capacitance is high, electrical inefficiencies and inaccuracies increase. It has been recognized that a reduction in capacitance within multi-level metallization system will reduce the RC time constant between the conductive lines.
The drive towards increased miniaturization and the resultant increase in the RC time constant have served as an impetus for the development of newer, low dielectric constant ("low k") materials as substitutes for conventional higher dielectric constant silicon oxide-based ILD materials. However, such dielectric materials must be able to serve a number of different purposes requiring diverse characteristics and attributes. For example, the ILD material must: prevent unwanted shorting of neighboring conductors or conducting levels by acting as a rigid, insulating spacer; prevent corrosion and/or oxidation of metal conductors, by acting as a barrier to moisture and mobile ions; fill deep, narrow gaps between closely spaced conductors; and undergo planarization of uneven surface topography so that a relatively flat level of conductors can be reliably deposited thereon. In addition, ILD films or layers must be formed at relatively low temperatures in order to avoid damage to or destruction of underlying conductors. Another, and important consideration in regard to RC time constant effects, is that such dielectric films used as ILD materials must have a low dielectric constant, as compared to the value of 3.9 of silicon dioxide (SiO.sub.2), in order to reduce the RC time constant, lower power consumption, reduce crosstalk, and reduce signal delay in closely spaced conductors.
Benzocyclobutene (BCB), a class of organic materials and derivatives thereof, manufactured by Dow Chemical Co., Midland, Mich., offers many advantages for use in multilevel interconnect technology. For example, BCB materials are resistant to diffusion by metals, such as copper (Cu) and gold (Au). Therefore, BCB materials can serve as a barrier to diffusion of contact metals. In addition, BCB materials exhibit very low values of dielectric constant (k), i.e., about 2.4 to 2.7, as compared to 3.9 to 4.1 of SiO.sub.2. Moreover, BCB materials can be applied by conventional spin-coating processing, resulting in good gap-filling and well planarized ILD layers.
However, a disadvantage associated with BCB-based dielectric materials applied by spin coating processes is the requirement for elevated temperature curing of the BCB-coated substrate in a separate oven or furnace. More specifically, conventional processing comprises applying a layer of BCB in fluid form (i.e., dissolved or dispersed in a solvent or dispersant liquid vehicle) to a substrate by spin coating, followed by baking at about 150.degree. C. to remove the solvent or dispersant. After such removal, conventional practices require curing the coated substrate at 250.degree. C. for 1 hour in a separate oven or furnace. Whereas the spin coating and solvent or dispersant removal steps can be performed in an automated fashion ("on track") by transport from a spin coating station to a "hot-plate" type baking station utilizing conventional track-type automated semiconductor processing apparatus, the removal of the baked wafers from the automated process track apparatus for curing treatment in a separate oven chamber for an extended time interval significantly reduces manufacturing throughput and, therefore, constitutes a significant drawback associated with the use of BCB-based ILD materials.
Thus, there exists a need for an "on track" process permitting utilization of BCB-based low k ILD materials in high-throughput automated, track-type semiconductor device manufacturing apparatus, particularly as employed in the manufacture of ultra large scale integration semiconductor devices having multiple metallization levels.